Field of the Disclosure
The present disclosure generally relates to designing of integrated circuits (ICs), and specifically to designing of ICs based on generation and instantiation or referencing of circuit stencils.
Description of the Related Arts
A design flow for ICs typically includes the steps of transistor-level design and simulation to generate a clean schematic design. The design flow further includes creating a layout for the simulated schematic and running layout-vs-schematic (LVS) checks and design rule checks (DRC) on the layout. LVS refers to determining whether a particular IC layout corresponds to the original schematic design, while DRC refers to determines whether the physical layout of a particular chip satisfies a series of recommended parameters called design rules. Circuit design flows are largely customized and lack full automation. Where IP re-use has been achieved, it has typically been of a ‘static’ or hardcoded form, thereby limiting its applications to only target locations that match the design source exactly. Alternate re-use approaches in the form of Module Generators require significant programming or scripting skills from the electronic design automation (EDA) vendor and/or the designer, and are thereby also equally limited in their application.